View MAX1162CEUB-T_7298735.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max1162 low-power, 16-bit analog-to-digital con- verter (adc) features a successive-approximation adc, automatic power-down, fast 1.1? wakeup, and a high- speed spi/qspi/microwire-compatible inter- face. the max1162 operates with a single +5v analog supply and features a separate digital supply, allowing direct interfacing with +2.7v to +5.25v digital logic. at the maximum sampling rate of 200ksps, the max1162 consumes only 2.5ma. power consumption is only 12.5mw (av dd = dv dd = +5v) at a 200ksps (max) sampling rate. autoshutdown reduces supply current to 130? at 10ksps and to less than 10? at reduced sampling rates. excellent dynamic performance and low power, com- bined with ease of use and small package size (10-pin ?ax and 10-pin dfn) make the max1162 ideal for battery-powered and data-acquisition applications or for other circuits with demanding power consumption and space requirements. applications motor control industrial process control industrial i/o modules data-acquisition systems thermocouple measurements accelerometer measurements portable- and battery-powered equipment features ? 16-bit resolution, no missing codes ? +5v single-supply operation ? adjustable logic level (+2.7v to +5.25v) ? input voltage range: 0 to v ref ? internal track/hold, 4mhz input bandwidth ? spi/qspi/microwire-compatible serial interface ? small 10-pin ?ax or 10-pin dfn package ? low power 2.5ma at 200ksps 130? at 10ksps 0.1? in power-down mode max1162 16-bit, +5v, 200ksps adc with 10a shutdown ________________________________________________________________ maxim integrated products 1 1 2 3 4 5 10 9 8 7 6 ain agnd dv dd dgnd cs agnd av dd ref max1162 max/dfn top view dout sclk pin configuration ordering information 19-2525; rev 0; 7/02 functional diagram appears at end of data sheet. for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package inl (lsb) max1162acub 0? to +70 c 10 ?ax 2 max1162ac_b* 0? to +70 c 10 dfn 2 max1162bcub 0 c to +70 c 10 ?ax 2 max1162bc_b* 0 c to +70 c 10 dfn 2 max1162ccub 0 c to +70 c 10 ?ax 4 max1162cc_b* 0 c to +70 c 10 dfn 4 max1162aeub -40 c to +85 c 10 ?ax 2 max1162ae_b* -40 c to +85 c 10 dfn 2 max1162beub -40 c to +85 c 10 ?ax 2 max1162be_b* -40 c to +85 c 10 dfn 2 max1162ceub -40 c to +85 c 10 ?ax 4 max1162ce_b* -40 c to +85 c 10 dfn 4 spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. autoshutdown is a trademark of maxim integrated products, inc. * future product?ontact factory for dfn package availability. evaluation kit available
max1162 16-bit, +5v, 200ksps adc with 10a shutdown 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = dv dd = +4.75v to +5.25v, f sclk = 4.8mhz (50% duty cycle), 24 clocks/conversion (200ksps), v ref = +4.096v, c ref = 4.7?, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd .........................................................-0.3v to +6v dv dd to dgnd.........................................................-0.3v to +6v dgnd to agnd.....................................................-0.3v to +0.3v ain, ref to agnd ...................................-0.3v to (av dd + 0.3v) sclk, cs to dgnd ..................................................-0.3v to +6v dout to dgnd .......................................-0.3v to (dv dd + 0.3v) maximum current into any pin ...........................................50ma continuous power dissipation (t a = +70?) 10-pin ?ax (derate 5.6mw/? above +70?) ..........444mw operating temperature ranges max1162_cub .................................................0? to +70? max1162_eub ..............................................-40? to +85? maximum junction temperature .....................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units dc accuracy (note 1) resolution 16 bits max1162a ? max1162b ? relative accuracy (note 2) inl max1162c ? lsb max1162a ? no missing codes over temperature max1162b -1 ?.75 differential nonlinearity dnl max1162c ? lsb transition noise rms noise ?.65 lsb rms offset error 0.1 1 mv gain error (note 3) ?.002 0.01 %fsr offset drift 0.4 ppm/ o c gain drift (note 3) 0.2 ppm/ o c dynamic specifications (1khz sine wave, 4.096v p-p ) (note 1) signal-to-noise plus distortion sinad 86 89.5 db signal-to-noise ratio snr 87 90 db total harmonic distortion thd -90 db spurious-free dynamic range sfdr 92 103 db full-power bandwidth -3db point 4 mhz full-linear bandwidth sinad > 86db 10 khz conversion rate conversion time t conv (note 4) 5 240 ? serial clock frequency f sclk 0.1 4.8 mhz aperture delay t ad 15 ns aperture jitter t aj <50 ps sample rate f s f sclk / 24 200 ksps track/hold acquisition time t acq 1.1 ?
max1162 16-bit, +5v, 200ksps adc with 10a shutdown _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = dv dd = +4.75v to +5.25v, f sclk = 4.8mhz (50% duty cycle), 24 clocks/conversion (200ksps), v ref = +4.096v, c ref = 4.7?, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units analog input (ain) input range v ain 0 v ref v input capacitance c ain 40 pf external reference input voltage range v ref 3.8 av dd v v ref = +4.096v, f sclk = 4.8mhz 100 v ref = +4.096v, sclk idle 0.01 input current i ref cs = dv dd , sclk idle 0.01 ? digital inputs (sclk, cs ) input high voltage v ih dv dd = +2.7v to +5.25v 0.7 x dv dd v input low voltage v il dv dd = +2.7v to +5.25v 0.3 x dv dd v input leakage current i in v in = 0 to dv dd ?.1 ? ? input hysteresis v hyst 0.2 v input capacitance c in 15 pf digital output (dout) output high voltage v oh i source = 0.5ma, dv dd = +2.7v to +5.25v dv dd - 0.25v v i sink = 10ma, dv dd = +4.75v to +5.25v 0.7 output low voltage v ol i sink = 1.6ma, dv dd = +2.7v to +5.25v 0.4 v three-state output leakage current i l cs = dv dd ?.1 ?0 ? three-state output capacitance c out cs = dv dd 15 pf power supplies analog supply av dd 4.75 5.25 v digital supply dv dd 2.7 5.25 v 200ksps 2.0 2.5 100ksps 1.0 10ksps 0.1 analog supply current i avdd cs = dgnd 1ksps 0.01 ma 200ksps 0.6 1.0 100ksps 0.3 10ksps 0.03 digital supply current i dvdd cs = dgnd, dout = all zeros 1ksps 0.003 ma
max1162 16-bit, +5v, 200ksps adc with 10a shutdown 4 _______________________________________________________________________________________ note 1: av dd = dv dd = +5v. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. note 3: offset and reference errors nulled. note 4: conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. note 5: defined as the change in positive full scale caused by a ?% variation in the nominal supply voltage. timing characteristics (figures 1, 2, 3, and 6) ( av dd = dv dd = +4.75v to +5.25v , f sclk = 4.8mhz (50% duty cycle), 24 clocks/conversion (200ksps), v ref = +4.096v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units acquisition time t acq 1.1 ? sclk to dout valid t do c dout = 50pf 50 ns cs fall to dout enable t dv c dout = 50pf 80 ns cs rise to dout disable t tr c dout = 50pf 80 ns cs pulse width t csw 50 ns cs fall to sclk rise setup t css 100 ns cs rise to sclk rise hold t csh 0ns sclk high pulse width t ch 65 ns sclk low pulse width t cl 65 ns sclk period t cp 208 ns timing characteristics (figures 1, 2, 3, and 6) (av dd = +4.75v to +5.25v, dv dd = +2.7v to +5.25v , f sclk = 4.8mhz (50% duty cycle), 24 clocks/conversion (200ksps), v ref = +4.096v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units acquisition time t acq 1.1 ? sclk to dout valid t do c dout = 50pf 100 ns cs fall to dout enable t dv c dout = 50pf 100 ns cs rise to dout disable t tr c dout = 50pf 80 ns cs pulse width t csw 50 ns cs fall to sclk rise setup t css 100 ns cs rise to sclk rise hold t csh 0ns sclk high pulse width t ch 65 ns sclk low pulse width t cl 65 ns sclk period t cp 208 ns electrical characteristics (continued) (av dd = dv dd = +4.75v to +5.25v, f sclk = 4.8mhz (50% duty cycle), 24 clocks/conversion (200ksps), v ref = +4.096v, c ref = 4.7?, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units shutdown supply current i avdd + i dvdd cs = dv dd , sclk = idle 0.1 10 ? power-supply rejection ratio psrr av dd = dv dd = +4.75v to +5.25v, full-scale input (note 5) 68 db
max1162 16-bit, +5v, 200ksps adc with 10a shutdown _______________________________________________________________________________________ 5 inl vs. output code max1162 toc01 output code inl (lsb) 52429 39322 13107 26214 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 0 65536 dnl vs. output code max1162 toc02 output code dnl (lsb) 52429 39322 26214 13107 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 06 5536 90 80 70 60 50 40 30 20 10 -120 -100 -80 -60 -40 -20 0 -140 0100 max1162 fft max1162 toc03 frequency (khz) magnitude (db) sinad vs. frequency max1162 toc04 frequency (khz) sinad (db) 10 1 10 20 30 40 50 60 70 80 90 100 0 0.1 100 sfdr vs. frequency max1162 toc05 frequency (khz) sfdr (db) 10 1 10 20 30 40 50 60 70 80 90 100 110 120 0 0.1 100 thd vs. frequency max1162 toc06 frequency (khz) thd (db) 10 1 0.1 100 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 10 0.01 0.1 1 10 100 1000 1 0.1 0.01 0.001 0.0001 supply current vs. conversion rate max1162 toc07 conversion rate (khz) supply current (ma) supply current vs. supply voltage max1162 toc08 supply voltage (v) supply current (ma) 5.15 5.05 4.95 4.85 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 4.75 5.25 supply current vs. temperature max1162 toc09 temperature ( c) supply current (ma) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 -40 85 t ypical operating characteristics (av dd = dv dd = +5v, f sclk = 4.8mhz, c load = 50pf, c ref = 4.7?, v ref = +4.096v, t a = +25?, unless otherwise noted.)
max1162 16-bit, +5v, 200ksps adc with 10a shutdown 6 _______________________________________________________________________________________ t ypical operating characteristics (continued) (av dd = dv dd = +5v, f sclk = 4.8mhz, c load = 50pf, c ref = 4.7?, v ref = +4.096v, t a = +25?, unless otherwise noted.) 0 4 2 8 6 12 10 14 18 16 20 4.75 4.85 4.95 5.05 5.15 5.25 max1162 toc10 supply voltage (v) i shdn (na) shutdown supply current vs. supply voltage shutdown supply current vs. temperature max1162 toc11 temperature ( c) shutdown supply current (na) 60 35 10 -15 50 25 100 75 150 125 0 -40 85 -1000 -400 -600 -800 -200 0 200 400 600 800 1000 4.75 4.95 4.85 5.05 5.15 5.25 offset error vs. analog supply voltage max1162 toc12 supply voltage (v) offset error ( v) -1000 -400 -600 -800 -200 0 200 400 600 800 1000 -40 10 -15 35 60 85 offset error vs. temperature max1162 toc13 temperature ( c) offset error ( v) -0.020 -0.015 -0.010 -0.005 0 0.005 0.010 0.015 0.020 4.75 4.85 4.95 5.05 5.15 5.25 gain error vs. analog supply voltage max1162 toc14 supply voltage (v) gain error (%) -0.020 -0.015 -0.010 -0.005 0 0.005 0.010 0.015 0.020 -40 -15 10 35 60 85 gain error vs . temperature max1162 toc15 temperature ( c) gain error (%)
detailed description the max1162 includes an input track-and-hold (t/h) and successive-approximation register (sar) circuitry to convert an analog input signal to a digital 16-bit out- put. figure 4 shows the max1162 in its simplest config- uration. the serial interface requires only three digital lines (sclk, cs , and dout) and provides an easy interface to microprocessors (?s). the max1162 has two power modes: normal and shut- down. driving cs high places the max1162 in shut- down, reducing the supply current to 0.1? (typ), while pulling cs low places the max1162 in normal operating mode. falling edges on cs initiate conversions that are driven by sclk. the conversion result is available at dout in unipolar serial format. the serial data stream consists of eight zeros followed by the data bits (msb first). figure 3 shows the interface timing diagram. analog input figure 5 illustrates the input sampling architecture of the adc. the voltage applied at ref sets the full-scale input voltage. track-and-hold (t/h) in track mode, the analog signal is acquired on the internal hold capacitor. in hold mode, the t/h switches open and the capacitive dac samples the analog input. during the acquisition, the analog input (ain) charges capacitor c dac . the acquisition interval ends on the falling edge of the sixth clock cycle (figure 6). at this instant, the t/h switches open. the retained charge on c dac represents a sample of the input. in hold mode, the capacitive digital-to-analog converter (dac) adjusts during the remainder of the conversion cycle to restore node zero to zero within the limits of 16-bit resolution. at the end of the conversion, force cs high and then low to reset the input side of the c dac switches back to ain, and charge c dac to the input signal again. the time required for the t/h to acquire an input signal is a function of how quickly its input capacitance is charged. if the input signal? source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. the acquisition time (t acq ) is the maximum time the device takes to acquire the signal. use the following formula to calculate acqui- sition time: t acq = 13(r s + r in ) x 35pf where r in = 800 ? , r s = the input signal? source impedance, and t acq is never less than 1.1?. a source impedance less than 1k ? does not significantly affect the adc? performance. to improve the input signal bandwidth under ac condi- tions, drive ain with a wideband buffer (>4mhz) that can drive the adc? input capacitance and settle quickly. max1162 16-bit, +5v, 200ksps adc with 10a shutdown _______________________________________________________________________________________ 7 pin description pin name function 1 ref external reference voltage input. sets the analog voltage range. bypass to agnd with a 4.7? capacitor. 2av dd analog +5v supply voltage. bypass to agnd (pin 3) with a 0.1? capacitor. 3, 9 agnd analog ground. connect pins 3 and 9 together. place star ground at pin 3. 4 cs active-low chip-select input. forcing cs high places the max1162 in shutdown with a typical current of 0.1?. a high-to-low transition on cs activates normal operating mode and initiates a conversion. 5 sclk serial clock input. sclk drives the conversion process and clocks out data at data rates up to 4.8mhz. 6dout serial data output. data changes state on sclk? falling edge. dout is high impedance when cs is high. 7 dgnd digital ground 8dv dd digital supply voltage. bypass to dgnd with a 0.1? capacitor. 10 ain analog input
max1162 input bandwidth the adc? input tracking circuitry has a 4mhz small- signal bandwidth, so it is possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid aliasing of unwanted high-frequency signals into the frequency band of interest, use anti-alias filtering. analog input protection internal protection diodes, which clamp the analog input to av dd or agnd, allow the input to swing from agnd - 0.3v to av dd + 0.3v, without damaging the device. if the analog input exceeds 300mv beyond the sup- plies, limit the input current to 10ma. 16-bit, +5v, 200ksps adc with 10a shutdown 8 _______________________________________________________________________________________ sclk dout t css t ch t cl t dv t csh t csw t tr t do t cp cs timing not to scale. figure 3. detailed serial interface timing sclk dout agnd dgnd ain ref av dd dv dd dout sclk cs ain v ref +5v +5v 4.7 f 0.1 f 0.1 f gnd max1162 cs figure 4. typical operating circuit dout a) v ol to v oh b) high-z to v ol and v oh to v ol dout 1ma 1ma dgnd dgnd c load = 50pf c load = 50pf v dd figure 1. load circuits for dout enable time and sclk to dout delay time dout a) v oh to high-z b) v ol to high-z dout 1ma 1ma dgnd dgnd c load = 50pf c load = 50pf v dd figure 2. load circuits for dout disable time
digital interface initialization after power-up and starting a conversion the digital interface consists of two inputs, sclk and cs , and one output, dout. a logic high on cs places the max1162 in shutdown (autoshutdown) and places dout in a high-impedance state. a logic low on cs places the max1162 in the fully powered mode. to start a conversion, pull cs low. a falling edge on cs initiates an acquisition. sclk drives the a/d conversion and shifts out the conversion results (msb first) at dout. timing and control conversion-start and data-read operations are con- trolled by the cs and sclk digital inputs (figures 6 and 7). ensure that the duty cycle on sclk is between 40% and 60% at 4.8mhz (the maximum clock frequen- cy). for lower clock frequencies, ensure that the mini- mum high and low times are at least 65ns. conversions with sclk rates less than 100khz can result in reduced accuracy due to leakage. note: coupling between sclk and the analog inputs (ain and ref) may result in an offset. variations in frequency, duty cycle, or other aspects of the clock signal? shape result in changing offset. a cs falling edge initiates an acquisition sequence. the analog input is stored in the capacitive dac, dout changes from high impedance to logic low, and the adc begins to convert after the sixth clock cycle. sclk drives the conversion process and shifts out the conversion result on dout. sclk begins shifting out the data (msb first) after the falling edge of the 8th sclk pulse. twenty-four falling clock edges are needed to shift out the eight leading zeros and 16 data bits. extra clock pulses occurring after the conversion result has been clocked out, and prior to the rising edge of cs, produce trailing zeros at dout and have no effect on the converter operation. force cs high after reading the conversion? lsb to reset the internal registers and place the max1162 in shutdown. for maximum throughput, force cs low again to initiate the next conversion immediately after the specified minimum time (t csw ). note: forcing cs high in the middle of a conversion immediately aborts the conversion and places the max1162 in shutdown. output coding and transfer function max1162 16-bit, +5v, 200ksps adc with 10a shutdown _______________________________________________________________________________________ 9 c dac 32pf r in 800 ? hold hold c switch 3pf ain ref gnd zero capacitive dac auto-zero rail track track figure 5. equivalent input circuit cs sclk 20 16 24 12 14 8 6 dout d15 d14 d13 d12 d11 d10 d9 d1 d0 d8 d5 d4 d3 d2 d7 d6 t csh t tr t do t acq t css t ch t cl t dv figure 6. external timing diagram
max1162 t he data output from the max1162 is binary and figure 8 depicts the nominal transfer function. code transitions occur halfway between successive-integer lsb values (v ref = 4.096v and 1lsb = 63? or 4.096v/65536). applications information external reference the max1162 requires an external reference with a +3.8v and av dd voltage range. connect the external reference directly to ref. bypass ref to agnd (pin 3) with a 4.7? capacitor. when not using a low-esr bypass capacitor, use a 0.1? ceramic capacitor in parallel with the 4.7? capacitor. noise on the refer- ence degrades conversion accuracy. the input impedance at ref is 40k ? for dc currents. during a conversion the external reference at ref must deliver 100? of dc load current and have an output impedance of 10 ? or less. for optimal performance, buffer the reference through an op amp and bypass the ref input. consider the max1162? equivalent input noise (38? rms ) when choosing a reference. input buffer most applications require an input buffer amplifier to achieve 16-bit accuracy. if the input signal is multi- plexed, switch the input channel immediately after acqui- sition, rather than near the end of or after a conversion (figure 9). this allows the maximum time for the input buffer amplifier to respond to a large step change in the input signal. the input amplifier must have a slew rate of at least 2v/? to complete the required output voltage change before the beginning of the acquisition time. at the beginning of the acquisition, the internal sampling capacitor array connects to ain (the amplifier output), causing some output disturbance. ensure that the sampled voltage has settled before the end of the acquisition time. digital noise digital noise can couple to ain and ref. the conver- sion clock (sclk) and other digital signals active dur- ing input acquisition contribute noise to the conversion result. noise signals synchronous with the sampling interval result in an effective input offset. asynchronous signals produce random noise on the input, whose high-frequency components can be aliased into the fre- quency band of interest. minimize noise by presenting a low impedance (at the frequencies contained in the 16-bit, +5v, 200ksps adc with 10a shutdown 10 ______________________________________________________________________________________ complete conversion sequence conversion 0 conversion 1 powered up powered up powered down dout cs timing not to scale. figure 7. shutdown sequence output code full-scale transition 11 . . . 111 11 . . . 110 11 . . . 101 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 123 0 fs fs - 3/2lsb fs = v ref input voltage (lsb) 1lsb = v ref 65536 figure 8. unipolar transfer function, full scale (fs) = v ref , zero scale (zs) = gnd
noise signal) at the inputs. this requires bypassing ain to agnd, or buffering the input with an amplifier that has a small-signal bandwidth of several mhz, or prefer- ably both. ain has 4mhz (typ) of bandwidth. distortion avoid degrading dynamic performance by choosing an amplifier with distortion much less than the max1162? total harmonic distortion (thd = -102db at 1khz) at fre- quencies of interest. if the chosen amplifier has insuffi- cient common-mode rejection, which results in degraded thd performance, use the inverting configuration (posi- tive input grounded) to eliminate errors from this source. low temperature-coefficient, gain-setting resistors reduce linearity errors caused by resistance changes due to self- heating. to reduce linearity errors due to finite amplifier gain, use amplifier circuits with sufficient loop gain at the frequencies of interest. dc accuracy to improve dc accuracy, choose a buffer with an offset much less than the max1162? offset (1mv (max) for +5v supply), or whose offset can be trimmed while maintain- ing stability over the required temperature range. serial interfaces the max1162? interface is fully compatible with spi, qspi, and microwire standard serial interfaces. if a serial interface is available, establish the cpu? ser- ial interface as master, so that the cpu generates the serial clock for the max1162. select a clock frequency between 100khz and 4.8mhz: 1) use a general-purpose i/o line on the cpu to pull cs low. 2) activate sclk for a minimum of 24 clock cycles. the serial data stream of eight leading zeros fol- lowed by the msb of the conversion result begins at the falling edge of cs . dout transitions on sclk? falling edge and the output is available in msb-first max1162 16-bit, +5v, 200ksps adc with 10a shutdown ______________________________________________________________________________________ 11 a0 a1 clk change mux input here conversion in1 a0 a1 in2 in3 in4 out acquisition 4-to-1 mux ain cs max1162 cs timing not to scale. figure 9. change multiplexer input near beginning of conversion to allow time for slewing and settling
max1162 format. observe the sclk to dout valid timing characteristic. clock data into the ? on sclk? ris- ing edge. 3) pull cs high at or after the 24th falling clock edge. if cs remains low, trailing zeros are clocked out after the least significant bit (d0 = lsb). 4) with cs high, wait at least 50ns (t csw ) before start- ing a new conversion by pulling cs low. a conver- sion can be aborted by pulling cs high before the conversion ends. wait at least 50ns before starting a new conversion. data can be output in three 8-bit sequences or continu- ously. the bytes contain the results of the conversion padded with eight leading zeros before the msb. if the serial clock has not been idled after the lsb (d0) and cs has been kept low, dout sends trailing zeros. spi and microwire interfaces when using the spi (figure 10a) or microwire (figure 10b) interfaces, set cpol = 0 and cpha = 0. conversion begins with a falling edge on cs (figure 10c). three consecutive 8-bit readings are necessary to obtain the entire 16-bit result from the adc. dout data transitions on the serial clock? falling edge. the first 8-bit data stream contains all leading zeros. the second 8-bit data stream contains the msb through d8. the third 8-bit data stream contains d7 through d0. qspi interface using the high-speed qspi interface with cpol = 0 and cpha = 0, the max1162 supports a maximum f sclk of 4.8mhz. figure 11a shows the max1162 con- nected to a qspi master and figure 11b shows the associated interface timing. 16-bit, +5v, 200ksps adc with 10a shutdown 12 ______________________________________________________________________________________ cs sclk dout i/o sck miso spi v dd ss max1162 figure 10a. spi connections max1162 cs microwire sclk dout i/o sk si figure 10b. microwire connections dout* cs sclk 1st byte read 2nd byte read *when cs is high, dout = high-z msb high-z 3rd byte read lsb d1 d0 d7 d6 d5 d4 d3 d2 24 20 16 12 8 6 4 1 d15 d14 d13 d12 d11 d10 d9 d8 d7 0 0000000 timing not to scale. figure 10c. spi/microwire interface timing sequence (cpol = cpha = 0)
pic16 with ssp module and pic17 interface the max1162 is compatible with a pic16/pic17 micro- controller (?) using the synchronous serial-port (ssp) module. to establish spi communication, connect the controller as shown in figure 12a. configure the pic16/pic17 as system master, by initializing its synchronous serial-port control register (sspcon) and synchronous serial-port status register (sspstat) to the bit patterns shown in tables 1 and 2. in spi mode, the pic16/pic17 ? allows 8 bits of data to be synchronously transmitted and received simulta- max1162 16-bit, +5v, 200ksps adc with 10a shutdown ______________________________________________________________________________________ 13 cs qspi sclk dout cs sck miso v dd ss max1162 sck sdi gnd pic16/17 i/o sclk dout cs v dd v dd max1162 figure 11a. qspi connections figure 12a. spi interface connection for a pic16/pic17 dout* cs sclk *when cs is high, dout = high-z msb 20 16 d15 d14 d13 d12 d11 d10 d9 high-z d1 d0 24 12 14 8 6 d8 d5 d4 d3 lsb d7 d6 end of acquisition d2 figure 11b. qspi interface timing sequence (cpol = cpha = 0) control bit max1162 settings synchronous serial-port control register (sspcon) wcol bit7 x write collision detection bit sspov bit6 x receive overflow detect bit sspen bit5 1 synchronous serial-port enable bit: 0: disables serial port and configures these pins as i/o port pins. 1: enables serial port and configures sck, sdo, and sci pins as serial port pins. ckp bit4 0 clock polarity select bit. ckp = 0 for spi master mode selection. sspm3 bit3 0 sspm2 bit2 0 sspm1 bit1 0 sspm0 bit0 1 synchronous serial-port mode select bit. sets spi master mode and selects f clk = f osc / 16. table 1. detailed sspcon register contents x = don? care.
max1162 neously. three consecutive 8-bit readings (figure 12b) are necessary to obtain the entire 16-bit result from the adc. dout data transitions on the serial clock? falling edge and is clocked into the ? on sclk? rising edge. the first 8-bit data stream contains all zeros. the sec- ond 8-bit data stream contains the msb through d8. the third 8-bit data stream contains bits d7 through d0. definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-fit straight line fit or a line drawn between the endpoints of the transfer func- tion, once offset and gain errors have been nulled. the static linearity parameters for the max1162 are mea- sured using the endpoint method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1lsb. a dnl error specification of 1lsb guarantees no missing codes and a monotonic transfer function. aperture definitions aperture jitter (t aj ) is the sample-to-sample variation in the time between samples. aperture delay (t ad ) is the time between the falling edge of the sampling clock and the instant when the actual sample is taken. 16-bit, +5v, 200ksps adc with 10a shutdown 14 ______________________________________________________________________________________ control bit max1162 settings synchronous serial-port control register (sspstat) smp bit7 0 spi data input sample phase. input data is sampled at the middle of the data output time. cke bit6 1 spi clock edge select bit. data is transmitted on the rising edge of the serial clock. d/a bit5 x data address bit p bit4 x stop bit s bit3 x start bit r/w bit2 x read/write bit information ua bit1 x update address bf bit0 x buffer full status bit table 2. detailed sspstat register contents dout* cs sclk 1st byte read 2nd byte read *when cs is high, dout = high-z msb high-z 3rd byte read lsb d1 d0 d7 d6 d5 d4 d3 d2 24 20 16 12 d15 d14 d13 d12 d11 d10 d9 d8 0 0000000 d7 timing not to scale. figure 12b. spi interface timing with pic16/pic17 in master mode (cke = 1, ckp = 0, smp = 0, sspm3 - sspm0 = 0001) x = don? care.
signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (snr) is the ratio of the full-scale analog input (rms value) to the rms quanti- zation error (residual error). the ideal, theoretical mini- mum analog-to-digital noise is caused by quantization noise error only and results directly from the adcs res- olution (n bits): snr = (6.02 x n + 1.76)db in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five har- monics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequency? rms amplitude to the rms equivalent of all the other adc output signals, excluding the dc offset. effective number of bits effective number of bits (enob) indicate the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc error consists of quantiza- tion noise only. with an input range equal to the full- scale range of the adc, calculate the effective number of bits as follows: enob = (sinad - 1.76) / 6.02 figure 13 shows the effective number of bits as a func- tion of the max1162? input frequency. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude and v 2 through v 5 are the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of the rms amplitude of the fundamental (maximum signal component) to the rms value of the next largest fre- quency component. supplies, layout, grounding, and bypassing use pc boards with separate analog and digital ground planes. do not use wire-wrap boards. connect the two ground planes together at the max1162 (pin 3). isolate the digital supply from the analog with a low- value resistor (10 ? ) or ferrite bead when the analog and digital supplies come from the same source (figure 14). thd vvvv v = +++ ? ? ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 log sinad db signal noise distortion rms rms () log = + () ? ? ? ? ? ? ? ? 20 max1162 16-bit, +5v, 200ksps adc with 10a shutdown ______________________________________________________________________________________ 15 input frequency (khz) effective bits 10 1 2 4 6 8 10 12 14 16 0 0.1 100 enob vs. input frequency figure 13. effective number of bits vs. input frequency sclk dout agnd dgnd ain 10 ? ref av dd dv dd dout sclk cs ain v ref +5v 4.7 f 0.1 f 0.1 f gnd max1162 cs figure 14. powering av dd and dv dd from a single supply
max1162 constraints on sequencing the power supplies and inputs are as follows: apply agnd before dgnd. apply ain and ref after av dd and agnd are present. ?v dd is independent of the supply sequencing. ensure that digital return currents do not pass through the analog ground and that return-current paths are low impedance. a 5ma current flowing through a pc board ground trace impedance of only 0.05 ? creates an error voltage of about 250?, 4lsb error with a +4v full- scale system. the board layout should ensure that digital and analog signal lines are kept separate. do not run analog and digital (especially the sclk and dout) lines parallel to one another. if one must cross another, do so at right angles. the adcs high-speed comparator is sensitive to high- frequency noise on the av dd power supply. bypass an excessively noisy supply to the analog ground plane with a 0.1? capacitor in parallel with a 1f to 10? low-esr capacitor. keep capacitor leads short for best supply-noise rejection. 16-bit, +5v, 200ksps adc with 10a shutdown 16 ______________________________________________________________________________________ ain track and hold 16-bit sar adc control dv dd dgnd cs agnd av dd ref dout sclk max1162 output buffer functional diagram chip information transistor count: 12,100 process: bicmos
max1162 16-bit, +5v, 200ksps adc with 10a shutdown maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 17 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. 10lumax.eps package outline, 10l umax/usop 1 1 21-0061 rev. document control no. approval proprietary information title: top view front view 1 0.498 ref 0.0196 ref s 6 side view bottom view 0 0 6 0.037 ref 0.0078 max 0.006 0.043 0.118 0.120 0.199 0.0275 0.118 0.0106 0.120 0.0197 bsc inches 1 10 l1 0.0035 0.007 e c b 0.187 0.0157 0.114 h l e2 dim 0.116 0.114 0.116 0.002 d2 e1 a1 d1 min - a 0.940 ref 0.500 bsc 0.090 0.177 4.75 2.89 0.40 0.200 0.270 5.05 0.70 3.00 millimeters 0.05 2.89 2.95 2.95 - min 3.00 3.05 0.15 3.05 max 1.10 10 0.60.1 0.60.1 ? 0.500.1 h 4x s e d2 d1 b a2 a e2 e1 l l1 c gage plane a2 0.030 0.037 0.75 0.95 a1 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) note: contact factory for dfn package outline.

▲Up To Search▲

Price & Availability of MAX1162CEUB-T

	To Download MAX1162CEUB-T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .